As the designs of electronic systems such as communication, recording, and entertainment systems migrate toward greater utilization of digital circuits, the precise and rapid conversion of analog signals into a digital format has become an essential design element. For example, to preserve the visual quality of an incoming high-definition analog video signal, an integrated circuit to convert the signal into a digital format typically requires 10 bits of precision in the analog-to-digital converter (ADC), with 6 MHz of bandwidth.
ADCs are usually designed to operate with a fixed range of input voltages, such as −0.5 volt to 0.5 volt, and are generally designed using switched-capacitor circuit technology to preserve the analog-to-digital conversion accuracy. Switched-capacitor circuit technology is a preferred circuit approach in view of the substantial variations in practical semiconductor manufacturing processes which produce resistors, capacitors, and transistors in integrated circuits with very accurate areas for the circuit elements, but with substantial variations from lot to lot in device parameters, such as resistance or capacitance, the variations sometimes approaching or even exceeding 30%. For example, individual capacitors formed on a die may exhibit substantial capacitance variations from a nominal design value due to imprecise control of dielectric thickness, but all capacitors on the die will be formed with substantially identical areas, which is well controlled by a precise lithographic process. All the capacitors on the die will, nonetheless, have substantially the same dielectric thickness, resulting in all capacitors having essentially the same capacitance deviation. Thus, a capacitance ratio on a die is a precisely controlled variable, not the absolute capacitances. Resistances and certain transistor parameters show similar substantial variations depending on manufacturing process parameters and device operating temperature, but resistance ratios for similar elements on the same die can also be accurately maintained. Since the accuracy of an analog-to-digital conversion or an amplification gain using switched-capacitor technology depends primarily on ratios of capacitances and resistances, this technology, which is readily amenable to implementation with fine-line feature sizes and which readily accommodates mixed-signal implementations, has become the design approach of choice for high speed, high accuracy, integrated circuits.
A practical high-performance analog-to-digital conversion process typically provides conversion for an input voltage signal that is limited to a voltage range from zero volts to some upper, variable voltage limit. The upper voltage limit may vary, for example, between 0.5 volts and 2.0 volts. To preserve the accuracy of the analog-to-digital conversion process, the input voltage signal must first be adjusted with accurate gain and offset so that it falls within the operating voltage limits of the ADC, such as −0.5 to 0.5 volt.
FIG. 1 illustrates a block diagram of the prior art showing scaling and shifting of an analog voltage input signal so that it falls within a fixed voltage range of an ADC such as −0.5 to 0.5 volt. The clamp 102 is included in the circuit to prevent the input voltage signal from assuming negative values. The buffer 104 is typically configured with two source followers so that the circuit does not load the input signal source, and provides a balanced, two-rail output for high-frequency performance of the downstream portions of the circuit. The amplifier 106 is a switched-capacitor programmable-gain amplifier (PGA) with its gain controlled typically by a four-bit digital gain-code signal. The required gain of the PGA is controlled to vary as 1/Vmax in the present example, where Vmax is the upper voltage limit of the input voltage signal. A constant offset voltage, VOFFSET, shifts the output voltage of the PGA using a voltage summing process such as the summers 108 so that the signal presented to the analog-to-digital converter 110 falls symmetrically within the range of −0.5 to 0.5 volt, thereby making full use of the input operating voltage range of the ADC. The process of scaling and shifting of the input voltage signal preserves the data accuracy in the output signal 112 from the ADC for the number of bits provided for the conversion process. If the input signal is not scaled and shifted to make use of the full operating range of the ADC, the analog-to-digital conversion process would operate with a reduced effective number of bits in the conversion process, i.e., it would “waste” one or two bits of precision.
However, when using switched-capacitor circuit technology, substantial drive currents are required to couple certain circuit elements, such as to a voltage source producing an offset voltage, due to the charge transfer nature of switched-capacitor circuits. For example, a switched-capacitor circuit with a switching frequency of 165 MHz implemented in an integrated circuit with 0.13 μm feature size may require source currents that can exceed 10 mA to produce an offset voltage. Large drive currents from such a source raise difficult practicality and cost issues that must be assessed in view of common design objectives for generally reducing energy consumption for any electronic equipment, and particularly for extending battery life for portable equipment.
To obtain high accuracy using switched-capacitor circuit technology, with its capability for implementation with fine-line integrated circuit technology and its immunity to manufacturing process variations, the prior art uses a circuit arrangement for analog-to-digital conversion that voltage-shifts an input voltage using a high drive current. The high drive current substantially increases the power required by the circuit, which detracts from product acceptance, particularly for portable systems and systems that operate continuously.
Thus, what is needed in the art is a circuit arrangement for an analog-to-digital conversion process that provides high accuracy and wide bandwidth, that operates with a limited input voltage range, and that can retain the advantages of switched capacitor circuit technology without the need for an offset voltage with a substantial drive current to scale and voltage-shift an input voltage signal.